1. Description of the Related Art
A prior-art example of a pulse generating circuit used in producing the operating clock of a microcomputer is disclosed in the specification of Japanese Patent Application Laid-Open No. 5-299985, by way of example. The specification discloses a circuit arrangement in which noise considered to be a cause of malfunction when an oscillator circuit is connected to various circuits such as a microcomputer can be eliminated from an oscillation waveform. A digital low-pass filter for delaying a change in leading and trailing edges of an input to a frequency divider circuit is provided in front of the frequency divider circuit, which frequency-divides clock pulses that have been generated by the oscillator circuit and shaped by a waveform shaping circuit.
This conventional pulse generating circuit for producing the operating clock of a microcomputer is constructed as shown in FIG. 5.
A sine wave produced as a result of oscillation derived from an inverter gate 506 and crystal oscillating element 507 has its waveform shaped by a Schmitt trigger circuit 502. Noise in the signal whose waveform has thus been shaped is removed by a noise eliminating circuit 503, after which the signal undergoes frequency division in a frequency divider circuit 504.
A selector circuit 505 connected to the output sides of the noise eliminating circuit 503 and frequency divider circuit 504 selects the output signal from the frequency divider circuit 504 or the input signal to the frequency divider circuit 504. The signal that has been selected by the selector circuit 504 is a system clock serving as the operating clock of a microcomputer.
2. Discussion on the Prior Art
In the following, the problems encountered during the course of investigations toward the present invention will be discussed in detail.
The pulse generating circuit shown in FIG. 5 is based upon the construction set forth in the above-mentioned specification. However, the arrangement in which the frequency divider circuit outputs a plurality of frequency-divided output signals and the input signal to or an output signal from the frequency divider circuit is selected by the selector circuit and used as a system clock has been added onto the circuitry disclosed in the above-mentioned specification.
The operation for eliminating noise in the generation of the operating clock of the microcomputer in accordance with the above-mentioned example of the prior art will now be described.
The noise eliminating circuit 503 in FIG. 5 has a construction of the kind shown in FIG. 6 by way of example. The operation of the noise eliminating circuit shown in FIG. 6 will be described with reference to the signal waveform diagram of FIG. 7. A signal 703 shown in FIG. 7 is the signal from an output node 703 of a delay circuit 601 in FIG. 6, a signal 704 is the signal from an output node 704 of an AND gate 602, a signal 705 is the signal from an output node 705 of a NOR gate 603, and a signal 706 is the signal from an output node 706 of a NOR gate 604. The signal 706 is the input signal of an inverter 606.
As shown in FIGS. 6 and 7, the signal 704, which is obtained by delaying the leading edge of the input signal 701, is produced by the delay circuit 601, which has been set to a delay time T, and the AND gate 602. Further, a signal 705, which is the inverse of a signal obtained by delaying the trailing edge of the input signal 701, is produced by the delay circuit 601 and the NOR gate 603.
An output signal 702, which has been delayed by the time T with respect to the input signal 701, is obtained by a flip-flop circuit comprising NOR gates 604, 605, whose outputs and inputs are cross-connected, and the inverter 606. The delay circuit 601 comprises cascade-connected inverters 607, 608 and a capacitor 609 connected to the output of the inverter 607.
A case in which noise of a duration shorter than the delay time T of the delay circuit 601 is contained in the input signal 701 will be described with reference to FIG. 6 and the timing chart of FIG. 8. As shown in FIG. 8, a signal 801 is the input signal to the delay circuit 601, a signal 803 is the signal from the output node 703 of delay circuit 60 1, a signal 804 is the signal from the output node of AND gate 602, a signal 705 is the signal from the output node 705 of NOR gate 603, a signal 806 is the signal (the input signal to the inverter 606) from the output node 706 of NOR gate 604, and a signal 802 is the output signal of the inverter 606.
Noise (tpw1 in the input signal 801 of FIG. 8) having a high-level duration shorter than the delay time T of delay circuit 601 is eliminated by the delay circuit 601 and AND gate 602, and noise (tpw2 in the input signal 801 of FIG. 8) having a low-level duration shorter than the delay time T1 is eliminated by the delay circuit 601 and NOR gate 603. Accordingly, both types of noise are absent from the output signal 802.
The delay circuit 601 shown in FIG. 6 will be described in further detail. The capacitance 609 is parasitic capacitance such as the wiring capacitance and gate capacitance of a MOS transistor, and/or or capacitance artificially fabricated. The MOS transistor within the inverter gate 607 charges and discharges the capacitance 609. The time needed for charging and discharging decides the delay time of the delay circuit.
Accordingly, in order to decide the delay time T of the delay circuit 601, it will suffice to decide the capacitance of capacitor 609 as well as the gate width and gate length of the MOS transistor within the inverter gate 607.
However, the delay time is dependent upon voltage owing to the characteristic of the MOS transistor. The delay time shortens when the operating power supply voltage rises and lengthens when the operating power supply falls. Accordingly, the delay circuit 601 must be designed in such a manner that the waveform-shaped output signal of the oscillator can be passed even when the operating power supply voltage is at its minimum value.
With the above-described conventional circuit for generating pulses used as an operating clock, the delay time of the delay circuit used in the noise eliminating circuit lengthens when the operating power supply voltage declines, and for this reason it is necessary to adopt such a design that the original signal of the oscillator will not be eliminated when the operating power supply voltage is at its smallest value. As a result, the noise eliminating effect is diminished when the operating power supply voltage is high.
According to the specifications of a microcomputer having a wide range of operating power supply voltages, a highspeed operating clock is selected when the operating power supply voltage is high, thus enabling high-speed operation, and a low-speed operating clock is selected when the operating power supply voltage is low, thus enabling low-speed operation. Operation at maximum speed, namely operation performed when the operating power supply voltage is high, is most often selected by users.
However, as mentioned above, the noise eliminating effect is diminished when the operating power supply voltage is raised, and noise penetrates to the interior of the device as a result. This raises the possibility that the microcomputer will be caused to malfunction.